| D1 | 1 • | 16 | Vcc |
| Q1 | 2 | 15 | D0 |
| Q0 | 3 | 14 | MR |
| CPD | 4 | 13 | TCD |
| CPU | 5 | 12 | TCU |
| Q2 | 6 | 11 | PL |
| Q3 | 7 | 10 | D2 |
| GND | 8 | 9 | D3 |
| Pin | Symbol | Description |
|---|---|---|
| 1 | D1 | parallel data input |
| 2 | Q1 | count output |
| 3 | Q0 | count output |
| 4 | CPD | count-down clock input (low-to-high edge-triggered) |
| 5 | CPU | count-up clock input (low-to-high edge-triggered) |
| 6 | Q2 | count output |
| 7 | Q3 | count output |
| 8 | GND | ground |
| 9 | D3 | parallel data input |
| 10 | D2 | parallel data input |
| 11 | PL | parallel load (active low) |
| 12 | TCU | terminal count-up (carry; active low) |
| 13 | TCD | terminal count-down (borrow; active low) |
| 14 | MR | master reset |
| 15 | D0 | parallel data input |
| 16 | Vcc | supply voltage |
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.