74107

Dual J-K flip-flop with reset; negative-edge trigger

PDF datasheet

    
1J1 •14Vcc
1Q2131R
1Q3121CP
1K4112K
2Q5102R
2Q692CP
GND782J
    
PinSymbolDescription
11Jsynchronous input
21Qcomplement output
31Qtrue output
41Ksynchronous input
52Qtrue output
62Qcomplement output
7GNDground
82Jsynchronous input
92CPclock input (high-to-low, edge-triggered)
102Rasynchronous reset (active low)
112Ksynchronous input
121CPclock input (high-to-low, edge-triggered)
131Rasynchronous reset (active low)
14Vccsupply voltage

Specifications

(typical values under recommended operating conditions, unless specified)
ParameterValueUnit
Propagation delay, nCP to nQ16 (74HC)
16 (74HCT)
ns
Propagation delay, nCP to nQ16 (74HC)
18 (74HCT)
ns
Propagation delay, nR to nQ, nQ16 (74HC)
17 (74HCT)
ns
Maximum clock frequency78 (74HC)
73 (74HCT)
MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.