74112

Dual J-K flip-flop with set and reset; negative-edge trigger

PDF datasheet

    
1CP1 •16Vcc
1K2151RD
1J3142RD
1SD4132CP
1Q5122K
1Q6112J
2Q7102SD
GND892Q
    
PinSymbolDescription
11CPclock input (high-to-low, edge-triggered)
21Ksynchronous input
31Jsynchronous input
41SDasynchronous set; direct input (active low)
51Qtrue output
61Qcomplement output
72Qcomplement output
8GNDground
92Qtrue output
102SDasynchronous set; direct input (active low)
112Jsynchronous input
122Ksynchronous input
132CPclock input (high-to-low, edge-triggered)
142RDasynchronous reset; direct input (active low)
151RDasynchronous reset; direct input (active low)
16Vccsupply voltage

Specifications

(typical values under recommended operating conditions, unless specified)
ParameterValueUnit
Propagation delay, nCP to nQ, nQ17 (74HC)
19 (74HCT)
ns
Propagation delay, nSD to nQ, nQ15 (74HC)
15 (74HCT)
ns
Propagation delay, nRD to nQ, nQ18 (74HC)
19 (74HCT)
ns
Maximum clock frequency66 (74HC)
70 (74HCT)
MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.