74164

8-bit serial-in/parallel-out shift register


DSA	1 •	14	Vcc
DSB	2	13	Q7
Q0	3	12	Q6
Q1	4	11	Q5
Q2	5	10	Q4
Q3	6	9	MR
GND	7	8	CP

Pin	Symbol	Description
1	DSA	data input
2	DSB	data input
3	Q0	output
4	Q1	output
5	Q2	output
6	Q3	output
7	GND	ground
8	CP	clock input (low-to-high, edge-triggered)
9	MR	master reset input (active low)
10	Q4	output
11	Q5	output
12	Q6	output
13	Q7	output
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Qn	12 (74HC) 14 (74HCT)	ns
Propagation delay, MR to Qn	11 (74HC) 16 (74HCT)	ns
Maximum clock frequency	78 (74HC) 61 (74HCT)	MHz

Notes

Either DSA or DSB can be used as an active high enable for data entry through the other input.
Otherwise, Both inputs must be connected together or an unused input must be tied high.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.