74165

8-bit parallel-in/serial-out shift register


PL	1 •	16	Vcc
CP	2	15	CE
D4	3	14	D3
D5	4	13	D2
D6	5	12	D1
D7	6	11	D0
Q7	7	10	DS
GND	8	9	Q7

Pin	Symbol	Description
1	PL	asynchronous parallel load input (active low)
2	CP	clock input (low-to-high, edge-triggered)
3	D4	parallel data input
4	D5	parallel data input
5	D6	parallel data input
6	D7	parallel data input
7	Q7	complementary output from the last stage
8	GND	ground
9	Q7	serial output from the last stage
10	DS	serial data input
11	D0	parallel data input
12	D1	parallel data input
13	D2	parallel data input
14	D3	parallel data input
15	CE	clock enable input (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP, CE to Q7, Q7	16 (74HC) 14 (74HCT)	ns
Propagation delay, PL to Q7, Q7	15 (74HC) 17 (74HCT)	ns
Propagation delay, D7 to Q7, Q7	11 (74HC) 11 (74HCT)	ns
Maximum clock frequency	56 (74HC) 48 (74HCT)	MHz

Notes

The low-to-high transition of input CE should only take place while CP is high for predictable operation.
Either CP or CE should be high before the low-to-high transition of PL to prevent shifting the data when PL is activated.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.