74166

8-bit parallel-in/serial-out shift register


D_s	1 •	16	Vcc
D₀	2	15	PE
D₁	3	14	D₇
D₂	4	13	Q₇
D₃	5	12	D₆
CE	6	11	D₅
CP	7	10	D₄
GND	8	9	MR

Pin	Symbol	Description
1	D_s	serial data input
2	D₀	parallel data input
3	D₁	parallel data input
4	D₂	parallel data input
5	D₃	parallel data input
6	CE	clock enable input (active low)
7	CP	clock input (low-to-high, edge-triggered)
8	GND	ground
9	MR	asynchronous master reset (active low)
10	D₄	parallel data input
11	D₅	parallel data input
12	D₆	parallel data input
13	Q₇	serial output from the last stage
14	D₇	parallel data input
15	PE	parallel enable input (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q₇	15 (74HC) 20 (74HCT)	ns
Propagation delay, MR to Q₇	14 (74HC) 19 (74HCT)	ns
Maximum clock frequency	63 (74HC) 50 (74HCT)	MHz

Notes

The low-to-high transition of CE should only take place while CP is high for predictable operation.
A low on MR overrides all other inputs and clears the register asynchronously, forcing all bit positions to a low stage.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.