74175

Quad D-type flip-flop with reset; positive-edge trigger


MR	1 •	16	Vcc
Q₀	2	15	Q₃
Q₀	3	14	Q₃
D₀	4	13	D₃
D₁	5	12	D₂
Q₁	6	11	Q₂
Q₁	7	10	Q₂
GND	8	9	CP

Pin	Symbol	Description
1	MR	asynchronous master reset (active low)
2	Q₀	flip-flop output
3	Q₀	complementary flip-flop output
4	D₀	data input
5	D₁	data input
6	Q₁	complementary flip-flop output
7	Q₁	flip-flop output
8	GND	ground
9	CP	clock input (low-to-high, edge-triggered)
10	Q₂	flip-flop output
11	Q₂	complementary flip-flop output
12	D₂	data input
13	D₃	data input
14	Q₃	complementary flip-flop output
15	Q₃	flip-flop output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n, Q_n	17 (74HC) 16 (74HCT)	ns
Propagation delay, MR to Q_n	15 (74HC) 19 (74HCT)	ns
Maximum clock frequency	83 (74HC) 54 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.