74194

4-bit bidirectional universal shift register


MR	1 •	16	Vcc
D_SR	2	15	Q₀
D₀	3	14	Q₁
D₁	4	13	Q₂
D₂	5	12	Q₃
D₃	6	11	CP
D_SL	7	10	S₁
GND	8	9	S₀

Pin	Symbol	Description
1	MR	asynchronous master reset (active low)
2	D_SR	serial data input (shift right)
3	D₀	parallel data input
4	D₁	parallel data input
5	D₂	parallel data input
6	D₃	parallel data input
7	D_SL	serial data input (shift left)
8	GND	ground
9	S₀	mode control input
10	S₁	mode control input
11	CP	clock input (low-to-high, edge-triggered)
12	Q₃	parallel output
13	Q₂	parallel output
14	Q₁	parallel output
15	Q₀	parallel output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n	14 (74HC) 15 (74HCT)	ns
Propagation delay, MR to Q_n	14 (74HC) 15 (74HCT)	ns
Maximum clock frequency	102 (74HC) 77 (74HCT)	MHz

Notes

S₀ and S₁ are low; hold (do nothing)
S₀ low and S₁ high; shift left
S₀ high and S₁ low; shift right
S₀ and S₁ high; parallel load

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.