74299 - 8-bit universal shift register; 3-state

Pin	Symbol	Description
1	S0	mode select input
2	OE1	output enable (active low)
3	OE2	output enable (active low)
4	I/O6	parallel data input/output
5	I/O4	parallel data input/output
6	I/O2	parallel data input/output
7	I/O0	parallel data input/output
8	Q0	serial output (standard output)
9	MR	asynchronous master reset (active low)
10	GND	ground
11	DSR	serial data shift-right input
12	CP	clock input (low-to-high, edge-triggered)
13	I/O1	parallel data input/output
14	I/O3	parallel data input/output
15	I/O5	parallel data input/output
16	I/O7	parallel data input/output
17	Q7	serial output (standard output)
18	DSL	serial data shift-left input
19	S1	mode select input
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q0, Q7	20 (74HC) 19 (74HCT)	ns
Propagation delay, CP to I/On	20 (74HC) 19 (74HCT)	ns
Propagation delay, MR to Q0, Q7, I/On	20 (74HC) 23 (74HCT)	ns
Maximum clock frequency	50 (74HC) 46 (74HCT)	MHz

Notes

S1 and S0 are low; hold (do nothing)
S1 is high and S0 is low; shift left (DSL → Q7, Q7 → Q6...)
S1 is low and S0 is high; shift right (DSR → Q0, Q0 → Q1...)
S1 and S0 are high; parallel load (I/On → Qn)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.


S0	1 •	20	Vcc
OE1	2	19	S1
OE2	3	18	DSL
I/O6	4	17	Q7
I/O4	5	16	I/O7
I/O2	6	15	I/O5
I/O0	7	14	I/O3
Q0	8	13	I/O1
MR	9	12	CP
GND	10	11	DSR