7473

Dual J-K flip-flop with reset; negative-edge trigger

PDF datasheet

    
1CP1 •141J
1R2131Q
1K3121Q
Vcc411GND
2CP5102K
2R692Q
2J782Q
    
PinSymbolDescription
11CPclock input (high-to-low edge-triggered)
21Rasynchronous reset (active low)
31Ksynchronous K input
4Vccsupply voltage
52CPclock input (high-to-low edge-triggered)
62Rasynchronous reset (active low)
72Jsynchronous J input
82Qcomplement output
92Qtrue output
102Ksynchronous K input
11GNDground
121Qtrue output
131Qcomplement output
141Jsynchronous J input

Specifications

(typical values under recommended operating conditions, unless specified)
ParameterValueUnit
Propagation delay, nCP to nQ16 (74HC)ns
Propagation delay, nCP to nQ16 (74HC)ns
Propagation delay, nR to nQ, nQ15 (74HC)ns
Maximum frequency77 (74HC)MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.