|Maximum clock frequency||100 (74HC)|
- State changes of Qn outputs do not occur simultaneously.
- Setting both MR1 and MR2 high resets the counter to zero.
- For a 4-bit counter, connect Q0 to CP1, and apply count pulses to CP0.
- For a 3-bit counter, apply count pulses to CP1.
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.