7493

4-bit binary ripple counter


CP₁	1 •	14	CP₀
MR₁	2	13	NC
MR₂	3	12	Q₀
NC	4	11	Q₃
Vcc	5	10	GND
NC	6	9	Q₁
NC	7	8	Q₂

Pin	Symbol	Description
1	CP₁	clock input, 2nd, 3rd and 4th section (high-to-low edge-triggered)
2	MR₁	asynchronous master reset
3	MR₂	asynchronous master reset
4	NC	no connection
5	Vcc	supply voltage
6	NC	no connection
7	NC	no connection
8	Q₂	counter output
9	Q₁	counter output
10	GND	ground
11	Q₃	counter output
12	Q₀	counter output
13	NC	no connection
14	CP₀	clock input, 1st section (high-to-low edge-triggered)

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP₀ to Q₀	12 (74HC) 15 (74HCT)	ns
Maximum clock frequency	100 (74HC) 77 (74HCT)	MHz

Notes

State changes of Q_n outputs do not occur simultaneously.
Setting both MR₁ and MR₂ high resets the counter to zero.
For a 4-bit counter, connect Q₀ to CP₁, and apply count pulses to CP₀.
For a 3-bit counter, apply count pulses to CP₁.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.