| Pin | Symbol | Description |
|---|
| 1 | RAS | VRAM row address strobe |
| 2 | CAS | VRAM column address strobe |
| 3 | AD7 | VRAM address/data bus (least significant bit) |
| 4 | AD6 | VRAM address/data bus |
| 5 | AD5 | VRAM address/data bus |
| 6 | AD4 | VRAM address/data bus |
| 7 | AD3 | VRAM address/data bus |
| 8 | AD2 | VRAM address/data bus |
| 9 | AD1 | VRAM address/data bus |
| 10 | AD0 | VRAM address/data bus (most significant bit) |
| 11 | R/W | VRAM write strobe |
| 12 | GND | ground |
| 13 | MODE | CPU interface mode select (usu. a CPU address line) |
| 14 | CSW | CPU-VDP write strobe |
| 15 | CSR | CPU-VDP read strobe |
| 16 | INT | CPU interrupt output |
| 17 | CD7 | CPU data bus (least significant bit) |
| 18 | CD6 | CPU data bus |
| 19 | CD5 | CPU data bus |
| 20 | CD4 | CPU data bus |
| 21 | CD3 | CPU data bus |
| 22 | CD2 | CPU data bus |
| 23 | CD1 | CPU data bus |
| 24 | CD0 | CPU data bus (most significant bit) |
| 25 | RD7 | VRAM read data bus (least significant bit) |
| 26 | RD6 | VRAM read data bus |
| 27 | RD5 | VRAM read data bus |
| 28 | RD4 | VRAM read data bus |
| 29 | RD3 | VRAM read data bus |
| 30 | RD2 | VRAM read data bus |
| 31 | RD1 | VRAM read data bus |
| 32 | RD0 | VRAM read data bus (most significant bit) |
| 33 | Vcc | supply voltage |
| 34 | RESET/SYNC | reset (active low; when above +9V, sync input for ext. video) |
| 35 | B-Y | B-Y color difference output |
| 36 | Y | luminance/sync output |
| 37 | GROMCLK | VDP output clock; XTAL/24 |
| 38 | R-Y | R-Y color difference output |
| 39 | XTAL1 | crystal input |
| 40 | XTAL2 | crystal input |